Date of Award
Master of Science (MS)
Electrical and Computer Engineering (Holcomb Dept. of)
Jon C. Calhoun
Polar code is a novel and high-performance communication algorithm with the ability to theoretically achieving the Shannon limit, which has attracted increasing attention recently due to its low encoding and decoding complexity. Hardware optimization further reduces the cost and achieves better timing performance enabling real-time applications on resource-constrained devices. This thesis presents an area-efficient architecture for a successive cancellation (SC) polar decoder. Our design applies high-level transformations to reduce the number of Processing Elements (PEs), i.e., only log2 N pre-computed PEs are required in our architecture for an N-bit code.
We also propose a customized loop-based shifting register to reduce the consumption of the delay elements further. Our experimental results demonstrate that our architecture reduces 98.90% and 93.38% in the area and area-time product, respectively, compared to prior works.
Tan, Weihang, "VLSI Architecture for Polar Codes Using Fast Fourier Transform-Like Design" (2020). All Theses. 3369.