Date of Award
Master of Science (MS)
Melissa C Smith
Jon C Calhoun
Walter B Ligon
Custom accelerators are largely beneficial for compute intensive applications such as data encryption or floating point arithmetic. These accelerators allow for a very specific task to be offloaded to its own unit so that the rest of the pipeline is not overwhelmed by these complicated instructions. To further achieve speed, a custom accelerator can be offloaded to an FPGA while still being on the same die as the CPU. Intel had announced this new technology back in 2014 and recently at the end of 2020, AMD released a patent application describing a similar approach.
In this thesis, we present a tightly coupled accelerator for the Rocket core, a RISC-V core that was developed at the University of California, Berkeley. This accelerator allows the user to develop their own custom logic that is part of the five stage pipeline but is abstracted away from execution units. This tightly coupled accelerator allows the user custom R-type instructions in the RISC-V ISA to use for their own applications.
We test the generic accelerator with the following three test applications: AES, posit addition, and the Rocket core's ALU. All three applications execute without any additional latency and stalls the pipeline appropriately for instructions that execute in more than one clock cycle.
Le, Theresa Thao, "A Tightly Integrated Generic Instruction RISC-V Accelerator (TIGRA) for the Rocket Core" (2021). All Theses. 3595.