Date of Award

May 2021

Document Type


Degree Name

Master of Science (MS)


Computer Engineering

Committee Member

Melissa C Smith

Committee Member

Jon C Calhoun

Committee Member

Walter B Ligon


FPGAs facilitate the implementation of custom logic to accelerate specific compputing tasks. This custom logic can be paired with a traditional processor which will offload computationally intensive tasks to the custom logic for faster execution. This pairing may take the form of loosely-coupled co-processors or tightly-coupled, application-specific logic integrated into the processor and utilizing extensions to the instruction set architecture. Both models have disadvantages: the former incurs area overhead and latency as a result of the communication between processor and co-processor, while the specificity of the latter can complicate the development of both the custom logic and custom instructions.

The Tightly Integrated Generic RISC-V Accelerator (TIGRA) interface addresses these issues with an interface for custom logic that avoids latency by providing direct access to the processor's registers and whose generic nature simplifies the modification of custom logic and instructions. In this work, the TIGRA interface is implemented on the PicoRV32, a simple, synthesizable RISC-V processor. Three different custom logic test cases with corresponding custom instructions are implemented to test TIGRA: an AES-128 encryption core, PACoGen hardware for performing posit arithmetic operations, and logic for handling multiplication instructions. Simulation and synthesis results reveal an absence of any additional latency in the execution of instructions using TIGRA, as well as minimal area overhead.



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