Date of Award

12-2008

Document Type

Thesis

Degree Name

Master of Science (MS)

Legacy Department

Electrical Engineering

Committee Chair/Advisor

Wang, Pingshan

Committee Member

Pearson , L. Wilson

Committee Member

Zhu , Lin

Committee Member

Harrell , William Rod

Committee Member

Wang , Pingshan

Abstract

Broadband signal generator is an indispensable module for broadband Six-Port Reflectometer (SPR). To integrate a whole SPR system on a chip, the source must be compact. In this thesis, a three-stage voltage-controlled oscillator (VCO), using two parallel weak invertor-chain oscillators and sense amplifiers, is proposed and designed in a 0.13 µm CMOS process. These two parallel weak inverter-chain oscillators extend the low frequency operating range and the sense amplifiers expand the high frequency operation. The measurement results show that the oscillator can be tuned from 430 MHz to 12 GHz, which satisfies the targeted SPR operating frequency range.
In order to expand the operating frequency band of the SPR, an introduction of the tuning mechanisms is necessary. Inductors and capacitors are the two basic components for the circuit modules of an SPR. Varactors are provided by process vendors. In this thesis, a novel differential active inductor is proposed and implemented in a 0.13 µm CMOS process. The measured self-resonance frequency is 6 GHz, which is the highest self-resonance frequency published thus far for a differential inductor. The proposed structure is further improved by adding a symmetrical negative resistor. Post layout shows a 10 GHz self-resonance frequency.
A power divider is a common module in the SPR and microwave circuits. A new lumped-element power divider structure, which presents the strongest tolerance to parasitic resistors in capacitors and inductors, is proposed and analyzed in this thesis by even- and odd-mode method. Varactors and the above-mentioned active inductors are used to build the proposed power divider. The circuit is designed in 0.13 µm CMOS technology with a core area of 300 µm_265 µm. Post layout simulation yields a tuning range from 1 GHz to 7.5 GHz.

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