Date of Award

5-2010

Document Type

Thesis

Degree Name

Master of Science (MS)

Legacy Department

Computer Engineering

Advisor

Smith, Melissa C

Committee Member

Ligon , Walter

Committee Member

Brooks , Richard

Abstract

The Timing Module and Optical Communication Card (OCC) are used for acquisition of neutron event data by the instrument systems at the Spallation Neutron Source (SNS) neutron scattering facility. The instrument systems produce a very large flux of neutrons of varying energies over a short time period through the spallation process. The Timing Module and OCC require high-bandwidth communication to ensure high-speed data movement to the memory in the data collection system without loss of neutron data. The existing implementations use a standard PCI-X bus interface to transfer the data between the cards and the host computer. The data processing on the existing cards is implemented in a Xilinx Virtex-II FPGA. The bandwidth restrictions of the PCI-X bus and the logic constraints of the Virtex-II FPGA have resulted in limited capabilities of the instrument systems. New designs for the timing and communication modules that will improve performance, avoid data loss, and provide for future logic expansion are desired.
In this project, we redesign the Timing Module and OCC moving from a PCI-X to PCI-Express bus interface to improve the data acquisition bandwidth. The new design also uses a Xilinx Virtex-5 FPGA to allow more channels to be processed per card and provide for further expansion. Further, the Virtex-5 device also has an embedded PCI-Express Hard IP core. This internal core simplifies the Printed Circuit Board (PCB) design since there is no external PCI interface chip required and decreases the probability of errors between the PCI interface and user logic design. The Timing Module implements a simple PCI Express read and write for the data transfer. The OCC requires a higher data rate than the Timing Module and therefore uses a more complex bus master direct memory access (DMA) for the endpoint PCI-Express block, which allows for lower CPU utilization and higher performance.
New user logic interfaces were designed to integrate the PCI-Express endpoint with the Timing Module and the OCC logic designs. A single PCB was designed to function as both the Timing Module and OCC. The logic designs were verified by both functional simulation and in-system JTAG signal capture on the new PCB. The results indicate that our design provides efficient data transfer, higher throughput, and scalability, benefitting both modules and meeting design requirements.

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