Date of Award
7-2008
Document Type
Thesis
Degree Name
Master of Science (MS)
Legacy Department
Computer Engineering
Committee Chair/Advisor
Taha, Tarek
Committee Member
Schalkoff , Robert
Committee Member
Hoover , Adam
Abstract
Digital image processing is a widely used and diverse field. It is used in a broad array of areas such as tracking and detection, object avoidance, computer vision, and numerous other applications. For many image processing tasks, the computations can become time consuming. Therefore, a means for accelerating the computations would be beneficial. Using that as motivation, this thesis examines the acceleration of two distinctly different image processing applications. The first image processing application examined is a recent neocortex inspired cognitive model geared towards pattern recognition as seen in the visual cortex. For this model, both software and reconfigurable logic based FPGA implementations of the model are examined on a Cray XD1. Results indicate that hardware-acceleration can provide average throughput gains of 75 times over software-only implementations of the networks examined when utilizing the full resources of the Cray XD1. The second image processing application examined is matched filter-based position detection. This approach is at the heart of the automatic alignment algorithm currently being tested in the National Ignition Faculty presently under construction at the Lawrence Livermore National Laboratory. To reduce the processing time of the match filtering, a reconfigurable logic architecture was developed. Results show that the reconfigurable logic architecture provides a speedup of approximately 253 times over an optimized software implementation.
Recommended Citation
Rice, Kenneth, "FPGA ACCELERATION OF A CORTICAL AND A MATCHED FILTER-BASED ALGORITHM" (2008). All Theses. 418.
https://tigerprints.clemson.edu/all_theses/418