Date of Award

12-2007

Document Type

Thesis

Degree Name

Master of Science (MS)

Legacy Department

Electrical and Computer Engineering

Advisor

Harrell, Dr.William R

Committee Member

Poole , Dr.Kelvin

Committee Member

Bridgwood , Dr.Michael A

Abstract

In recent years, NAND flash memory has gained a lot of momentum in the semiconductor industry and has become an ideal choice for many consumer and communication products. One of the key elements in the successful production of NAND flash memory is to incorporate elaborate testing methods to ensure functionality and reliability before the part reaches the customer. This in turn necessitates the evaluation and understanding of different failure mechanisms, and the development of methodologies to correct problems.
In this thesis, failure analysis was performed on NAND flash memory at wafer and package level. This involved massive data collection and evaluation of failures at both the wafer level and package from several thousand parts using PERL scripts and software codes. In the process of analysis, a test for reading the flash memory resulted in unusually high failure rates at the package level. Failure data was collected in order to study the trends and correlations with various parameters such as applied voltage, the proximity of failures on a wafer, the cell characteristics of each failing die compared to good die, and the threshold voltage distribution. A series of tests and experiments indicated that the reason for the higher failure rate was due to the positioning of the test for programming time in the package test flow. This altered the threshold voltage distribution of the flash cells in a way that resulted in higher fails after the test for read. When the added test for programming time was moved to a different location the result was a decrease in failure rate. This study resulted in a fundamental understanding of the key issues in NAND flash memory. Even a very slight shift of the flash cell threshold voltage distribution can change the operation of the cell. Thus, failure analysis of NAND flash memory at wafer and package level presents methodologies and corrective actions which curb the occurrence of those kinds of failures for future products.

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